Xilinx’ Zynq UltraScale+ RFSoC chips integrate the RF signal chain

October 04, 2017 //By Graham Prophet
Xilinx’ Zynq UltraScale+ RFSoC chips integrate the RF signal chain

Following a recent announcement of the technology, Xilinx has announced that it is now shipping its RFSoC family devices, that it presents as a means of saving power and space, by integrating many functions – particularly high-speed ADCs and DACs – alongside programmable logic and other ‘hard’ function blocks.

 

As part of the announcement, Xilinx has fleshed out the details of the configuration of the SoCs in the family, that shapes them for their intended markets of 5G Wireless, Cable Remote-PHY, and Radar.

 

 

Based on 16nm UltraScale+ MPSoC architecture, the all-programmable RFSoCs monolithically integrate RF data converters for up to 50-75% system power and footprint reduction, and soft-decision Forward Error Correction (SD-FEC) cores to meet 5G and DOCSIS 3.1 standards. An early access program for the Zynq UltraScale+ RFSoC family is now available.

 

Zynq RFSoCs combine RF data converters and SD-FEC cores with high performance 16nm UltraScale+ programmable logic and ARM® multi-processing system to create a comprehensive analogue-to-digital signal chain. While RF to digital signal conditioning and processing is typically segmented into stand-alone subsystems, the Zynq UltraScale+ RFSoC brings analogue, digital, and embedded software design onto a single monolithic device for system robustness. Devices in the family feature:

- Eight 4 GSPS or sixteen 2GSPS 12-bit ADCs

- Eight to sixteen 6.4GSPS 14-bit DACs

- Integrated SD-FEC cores with LDPC and Turbo codecs for 5G and DOCSIS 3.1

- ARM processing subsystem with Quad-Core Cortex-A53 and Dual-Core Cortex-R5s

- 16nm UltraScale+ programmable logic with integrated Nx100G cores

- Up to 930,000 logic cells and over 4,200 DSP slices

Alongside this list, Xilinx emphasises that these are monolithic devices; they do not use the company’s “2 ½-D” multi-chipo-plus-interposer technology.

 

Power savings come from a variety of sources, but in particular, a less integrated design will required high-bandwidth interfaces from data converter to FPGA – typically, JESD204B serial links. On-chip connectivity reduceds the power burden of transmitting


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