The world’s most powerful DSP architecture

March 09, 2020 //By Ally Winning
CEVA has launched Gen4 CEVA-XC, which the company claims is the world’s most powerful DSP architecture.
CEVA has launched Gen4 CEVA-XC, which the company claims is the world’s most powerful DSP architecture.

Gen4 CEVA-XC brings together scalar and vector processing principles in an architecture that provides two-times 8-way VLIW and up to 14,000 bits of data-level parallelism. It uses a deep pipeline architecture that allows operating speeds of 1.8 GHz at a 7nm process node with a unique physical design architecture for a fully synthesizable design flow, and an innovative multithreading design. The architecture allows the processors to be dynamically reconfigured as either a wide SIMD machine or divided into smaller simultaneous SIMD threads. The Gen4 CEVA-XC uses a memory subsystem with 2048-bit memory bandwidth and coherent, tightly-coupled memory to support simultaneous multithreading and memory access.

The first new processor that has been based on the Gen4 CEVA-XC architecture is the multicore CEVA-XC16. It is targeted for the rapid deployment of different form factors of 5G RAN architectures. CEVA-XC16 is also applicable to massive signal processing and AI workloads associated with base station operation.

The CEVA-XC16 has been specifically architected with the latest 3GPP release specifications in mind. The processor offers high parallelism of up to 1,600 Giga Operations Per Second (GOPS) that can be reconfigured as two separate parallel threads. The threads can run simultaneously, sharing L1 Data memory with cache coherency. The new concepts boost the performance per square millimetre by 50% compared to a single-core/single-thread architecture.

Additional key features of CEVA-XC16:

- Latest generation dual CEVA-BX scalar processor units

- Dynamic allocation of vector units resources to processing threads

- Advanced scalar control architecture and tools, with 30% code size reduction from previous generations, using latest dynamic branch prediction and loop optimizations, and an LLVM based compiler

- New Instruction Set Architectures for FFT and FIR - delivering 2X performance improvement

- Enhanced multiuser capabilities supporting massive bandwidth allocation of single user as well as fine granularity user allocations

- Simple software migration path from previous generations CEVA-XC4500 and CEVA-XC12 DSPs

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