At the RISC-V Summit 2018 Western Digital announced three new open-source innovations. In his keynote address, Western Digital’s Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator. These three innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments.
RISC-V is an open, scalable instruction set architecture that enables the diversity of Big Data and Fast Data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge. It provides an alternative to current, standard, general purpose compute architectures. With RISC-V, open standard interfaces can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications.
Western Digital is planning to open source its new RISC-V SweRV Core, which has a 2-way superscalar design. Western Digital’s RISC-V SweRV Core is a 32-bit, 9 stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs. It is a compact, in-order core and runs at 4.9 CoreMarks/Mhz1. Its power-efficient design offers clock speeds of up to 1.8Ghz1 on a 28mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.