Imec in Belgium has developed a test chip using a new technique that dramatically reduces the power of machine learning edge AI systems.
The Analog in Memory Computing (AiMC) architecture uses modified memory cells to process data in trained neural networks for AI at the edge of the network with a power efficiency of 2900TOPS/W.
“We have built a special compute cell where you are saving energy by reducing the digital transfers,” said Diederik Verkest, program director for machine learning at imec. “Depending on the pulse width on the activation line [of the cell] you get summation of the weights on the [analog to digital converter] ADC before continuing with digital computations,” he said
“The successful tape-out of AnIA marks an important step forward toward validation of Analog in Memory Computing (AiMC),” said Verkest. “The reference implementation not only shows that analog in-memory calculations are possible in practice, but also that they achieve an energy efficiency ten to hundred times better than digital accelerators. From our perspective this was a milestone in the machine learning programme to show that an analogue computation can have the same accuracy as digital computation”
The Analog Inference Accelerator (AnIA) test chip has been built on the 22nm FD-SOI low power process from Global Foundries at its fab in Dresden, Germany. The chip is 4mm2 with 1024 input signals and 512 outputs with similar performance to today’s graphics processing units (GPUs). It showed the same accuracy as a digital implementation to within 1 percent but had a power efficiency of 2900TOPS/W. The combination of low power and low cost opens up opportunities for edge AI image recognition and sensing in embedded hardware.
“Analogue compute is a phenomenal frontier as it allows you to reduce the data movement and this is going to become mainstream,” said Hiren Majmudar, vice president of product management for computing and wired infrastructure at GF.