SweRV RISC-V CoreTM from Western Digital now on Github

January 30, 2019 //By Wisse Hettinga
SweRV RISC-V CoreTM from Western Digital now on Github
Github repository contains the SweRV CoreTM design RTL

At the latest RISC-V workshop Martin Fink CTO of Western Digital, delivered a keynote entitled, “Unleashing Innovation from Core to the Edge,” punctuated by three new Western Digital developed open-source innovations. These efforts are designed to support the company’s desire for open standard interfaces, our internal RISC-V development needs and those of the growing RISC-V ecosystem. These included plans to release to the open source community Western Digital’s first RISC-V core, the SweRV Core™, as well as the immediate availability of the OmniXtend™ specification for cache coherent memory over a network and the SweRV ISS™ (Instruction Set Simulator). These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments.

On GitHub the SweRV Core design is now available https://github.com/westerndigitalcorporation/swerv_eh1

Or check the eeNews Interview with Martin Fink at the RISC-V workshop 2018 in Barcelona. https://www.eenewsembedded.com/content/clone-value-data-eenews-interview...


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