Spinout funded for RISC-V edge AI chip

December 22, 2020 //By Peter Clarke
Swiss spin-off to develop RISC-V edge AI chip
ETH spinout Synthara in Switzerland has raised seed funding for an edge AI chip design based on the RISC-V instruction set architecture.

Synthara in Switzerland is developing a dual-core RISC-V edge AI chip with an integrated Adaptiva accelerator for AI workloads.

No indication is given of the target manufacturing process node for the AdaptiveStorm chip, but in watchdog mode the power consumption of the Adaptiva acelerator will be less than 1mW and less than 1-microwatt in some use cases and when running offer up to 10TOPS/W, according to the company's website. As with other systems, there is also a strong focus on the tools that allow the edge AI chip to handle a range of machine learning frameworks (above).

The size of the funding round was not disclosed but is being led by High-Tech Gründerfonds. The company was founded by Manu Nair, Alessandro Aimar and Iulia-Alexandra Lungu and is a spin-off from the UZH-ETH Institute of Neuroinformatics (INI) in Zurich, Switzerland.

Adaptiva is designed to support convolutional neural networks such as resNet, VGG and MobileNet and recurrent neural networks with multiple layers. The edge AI chip will be designed to support sensor fusion and interpretation with standard audio and video interfaces including MIPI, I2C, SPI and direct interfaces to raw sensor data such as microphones, audio and accelerometers.

Synthara is also going to engineering lengths to make sure its chip is easy to use and program. Synthara is preparing compiler libraries that optimize for energy-efficiency. Developers can use popular AI libraries such as PyTorch or Tensorflow to train neural networks. These networks will be ported to Adaptiva by compilers, which also handles workload planning to ensure maximum energy-efficiency. Direct writing to Adaptiva of machine learning algorithms can be performed by Synthara staff.

Aimar, CTO of the company, said Adaptiva makes use of both sparsity-aware processing and in-memory computation "Our algorithm-aware chips are designed to deliver up to 500 times better performance for the next generation of smart sensor applications that use inertial measurement units, audio and


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