To design the 500 square millimetre chip took a team of up to 200 engineers, often working on it simultaneously.
“This initially started out as a design for 28nm technology,” explained Stuart Vernon, Sondrel’s Senior Director of Physical Design. “However, it soon became apparent that, on 28nm, it would either be one very big chip, which would not have been cost effective, or it would have to be be split into two connected chips, which would introduce parasitics and timing issues. So the decision was made to use the 16nm TSMC process node to enable the design to fit onto a single chip at a cost effective price point.”
Around a third of the chip’s floor plan was the block that contained the customer’s IP, which handles the real-time image processing. That block was supported by blocks of Graphical Processor Unit, two Central Processor Units, on-chip cache memory, PCI and USB interfaces plus memory controllers to off-chip memory. Over 7 kilometres of metal tracks were used on a chip the size of a postage stamp.
The chip had 300 million placeable logic cells, and the placement tool that Sondrel used could only handle 3 million at a time without the runtime becoming excessive. The IC was then divided into manageable-sized, functional blocks over four levels of a hierarchy structured like a pyramid. This allowed the block design to be partitioned between Sondrel’ s worldwide design teams. As each block was finished, the y were brought together by creating abstract models of the lower blocks to provide input for the higher blocks so that the size of the part of design being implemented remained manageable. As the chip can run at up to 100 Watts, even the heat output of the different parts of the chip ha d to be allowed for in the design to prevent hotspots
When all the component blocks were integrated, the complete design was