The standard is backward compatible with specification 2.0 allowing the new features to be either multiplexed with existing signals or implemented as additions that do not compromise edge connector pins assigned in the 2.0 specifications.
Major updates include:
- 4 MIPI CSI port support for the AI and Robotics markets
- Multiplexing of SERDES signals over the 3rd and 4th PCIe x1 interfaces for additional Ethernet ports
- Minor additions over earlier reserved pins such as plus 2 GPIO pins and PCIe clock request signals
The 4 native CSI MIPI camera inputs is designed to help integrate SOCs that feature integrated Neural Processing Units (NPUs) and multiple camera inputs for video-based AI solutions. The third and fourth camera port are implemented through FFC feature connectors on the module, with each able to support up to 4 MIPI CSI data lanes. This positions SMARC as the preferred standard for scalable, low power, silicon independent AIoM (AI on Module) solutions.
Multiplexing SERDES signals over the 3rd and 4th PCIe x1 interfaces adds support for an additional two Ethernet ports - potentially allowing a module to work with up to 4 GbE Ethernet ports.
The specification itself had a major structural overhaul for readability. Attention has been to supply precise and detailed information about every pin’s power domain and PU/PD status. This will simplify carrier board designs and it will increase the level of compatibility and interoperability between module designs.