Siemens and ASE enable high density advanced package designs

February 12, 2021 // By Jean-Pierre Joosting
Siemens and ASE enable high density advanced package designs
Create and evaluate multiple complex IC package assemblies and interconnect scenarios in an easy-to-use, data-robust graphical environment

A collaboration between Siemens Digital Industries Software and Advanced Semiconductor Engineering (ASE) has generated two new enablement technologies engineered to help mutual customers create and evaluate multiple complex IC package assemblies and interconnect scenarios in an easy-to-use, data-robust graphical environment prior to and during physical design implementation.

The new high-density advanced packaging (HDAP) enablement technologies stem from ASE’s participation in the Siemens OSAT Alliance – a program designed to drive faster adoption of new HDAP technologies like 2.5D, 3D IC and Fan-Out wafer-level packaging (FOWLP) for next-generation IC designs. ASE is a leading  provider of independent semiconductor assembling and test manufacturing services.

ASE’s latest achievements as part of the OSAT Alliance include an assembly design kit (ADK) that helps customers using ASE’s Fan Out Chip on Substrate (FOCoS) and 2.5D Middle End of Line (MEOL) technologies to fully leverage the Siemens HDAP design flow. ASE and Siemens have also agreed to extend their partnership to include the future creation of a single design platform from FOWLP to 2.5D substrate design. All of these joint initiatives leverage Siemens’ Xpedition™ Substrate Integrator software and Calibre® 3DSTACK platform.

“By adopting the Siemens Xpedition Substrate Integrator and Calibre 3DSTACK technologies, and through integration with the current ASE design flow, we can now leverage this mutually developed flow to significantly reduce 2.5D/3D IC and FOCoS package assembly planning and verification cycle times by about 30 to 50 percent in each design iteration,” said Dr. C.P. Hung, vice president, ASE Group. “Through the comprehensive design flow, we can now more quickly and easily co-design with our customers for 2.5D/3D IC and FOCoS design and close any physical verification issues for their entire wafer package assembly.”


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