RV32E Floating-Point library offers 72% code size reduction

September 21, 2020 //By Ally Winning
SEGGER has released a new version of the RISC-V Floating-Point Library that offers full support for the RV32E embedded variant of the RISC-V core.
SEGGER has released a new version of the RISC-V Floating-Point Library that offers full support for the RV32E embedded variant of the RISC-V core.

The new library has been developed to reduce the code size for RISC-V applications that use floating-point. The reduction in memory footprint of RISC-V applications is realised by having all arithmetic functions using floating-point code hand-coded in assembly language. The Floating-Point library was designed to comply with the RISC-V ABI standard. This compliance means that the library can be easily used as a plug-and-play replacement for any other floating-point library.

Replacing the GNU floating-point library that is used by most toolchains with the SEGGER assembly optimized library can provide a code size reduction of over 72% in the benchmark application. The library supports both the RV32I and the newly introduced RV32E embedded variant of the RISC-V core with the assembly-level code.

"This new release is much smaller than anything available to us for comparison and, at the same time, is incredibly fast,” says Rolf Segger, Founder of SEGGER. "In the world of Embedded Systems, every byte counts. The SEGGER Floating-Point library delivers high performance and uses the architectural advantages of RISC-V to close the code-density gap to comparable Arm Cortex devices. We are convinced that our software is market-leading and – unlike some of our competitors – we facilitate and encourage comparing and benchmarking it.”

The library can be licensed by end customers and toolchain suppliers. Similarly to the SEGGER Runtime Library, it is integrated into SEGGER Embedded Studio for RISC-V. Using Embedded Studio, benchmarking for both floating-point and runtime libraries can be done quickly and easily. The library is available free of charge for non-commercial usage under SEGGER’s Friendly License.

More information

https://blog.segger.com/profiling-and-code-coverage-on-risc-v-using-simulation/

https://www.segger.com/risc-v/

Related news

Cutting code size with SEGGER Embedded Studio V5

Audio added to SEGGER emUSB-Host

SEGGER launches    third product in    emCompress software range

SEGGER Ports embOS for RISC-V Architecture


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.