The new solution is based on Aldec’s HES-MPF500-M2S150 prototyping board.
“Aldec has a long history of developing hardware assisted verification solutions, with our first HES board and simulation acceleration platform released 20 years ago,” said Zibi Zalewski, General Manager of Aldec’s Hardware Division. “We also have a proven track record of developing Microsemi/Microchip FPGA prototyping boards, and it is great that we can combine these areas of expertise to meet today’s verification challenges.”
Most simulation acceleration techniques are based on FPGAs from one or two FPGA vendors. Normally w hich FPGA family is used on the simulation acceleration board doesn’t really matter too much as the design will be coded using synthesizable RTL.
However, a growing number of designs are increasing in complexity, which is compounded by the pressing need for shorter design cycles and a desire to get to market quicker. This has led to an increasing amount of engineers making use of re-usable IP blocks from the FPGA vendor, instead of developing the RTL code themselves. Th at means that the developers are locked into the given FPGA technology. These re-usable IP blocks normally need much more computational power to simulate than pure RTL code.
Aldec’s HES-DVM was developed to overcome these challenges and remove a key verification bottleneck. The new release of th e EDA tool allows users of PolarFire, RTAX/RTSX and SmartFusion2 devices to take advantage of Microchip IPs to accelerate RTL simulations with Aldec’s HES-MPF500-M2S150. The board is based around the largest devices available in both families.
Zalewski concludes: “During the 20 years since we introduced HES, the world of digital designs has changed significantly and the need for simulation speeds to increase has grown along with not only design complexity but also the size and features of FPGAs. Our latest release of HES-DVM will be of great benefit to designers using Microchip IPs.”