Renesas cuts embedded SRAM standby power in prototype technology

June 12, 2017 //By Graham Prophet
Renesas cuts embedded SRAM standby power in prototype technology
Renesas reports that it has developed a very-low-power SRAM circuit technology that can be embedded in ASSPs for IoT, healthcare and other low power applications. The technology provides a function for switching dynamically, with low power overhead, between active operation in which the CPU core performs read and write operations to the embedded SRAM, and the standby mode in which the stored data is retained.

This enables Renesas to quote standby power of 13.7 nW/Mbit and 1.84 nsec high-speed readout. Renesas applied its in-house 65 nm-node silicon on thin buried oxide (BOX or SOTB) process for the prototype development of the embedded SRAM. The prototype SRAM achieves simultaneous high-speed readout during active operation, and ultra-low power consumption in standby mode. The SRAM takes advantage of the SOTB structure by using dynamic substrate back bias control to achieve the lowest standby-mode power consumption, which is only one-thousandth of the power consumption during normal standby mode.

 

The SRAM would be used in an intermittent mode providing storage at near-non-volatile-memory power levels, but without the power expenditure needed to save to NVM prior to shutdown.

 

Previous Renesas efforts related to embedded SRAM include prototype of an embedded SRAM with a 28-nm high-K metal gate (HKMG) structure and a high-performance embedded SRAM with a 16-nm Fin field-effect transistor (FinFET) structure, which both adopt state-of-the-art process technologies. These embedded SRAM technologies have been adopted in Renesas’ R-Car automotive infotainment system-on-chips (SoCs). Now, to achieve the low-power performance required for IoT, home electronics, and healthcare applications, Renesas developed circuit technology that dynamically controls the substrate bias using the SOTB process technology and enables standby mode leakage current to be reduced to approximately one-thousandth of the power compared to the normal standby mode.

 

The SOTB process technology differs from the planar transistor structure formed on the silicon substrate in earlier process technologies as an oxide film (BOX: buried oxide) is buried under a thin silicon layer on the wafer substrate. The technology enables dopant-less channel transistors that do not require doping the thin-film silicon layer. By making the structure a dopant-less channel structure, the variations in the transistor threshold characteristics can be reduced to approximately one-third those of the earlier planar type bulk structure transistors. This reduction in variations has a similar effect to the FinFET structure adopted in


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.