Questa verification solution accelerates aerospace FPGA development

October 12, 2018 // By Ally Winning
Leonardo has accelerated its FPGA design cycle, using the advanced verification techniques found in Mentor’s Questa verification solution.

Leonardo has been using Mentor’s Questa SystemVerilog verification solution, applying the Universal Verification Methodology (UVM) framework and Questa Verification IP (QVIP) to the design, verification and validation (V&V) of highly complex avionics interfaces. Results achieved to date indicate an acceleration of the design, V&V and system integration phases of a key product.

Incorporation of the UVM framework, QVIP and Verification Run Manager into a Jenkins software-based environment has extracted further value from the toolkit, enabling automated reverification of designs, post modification.

Mentor QVIP provides an easy-to-use library of verification IP for more than 40 standard protocols and 1,700 memory devices. QVIP includes checkers and coverage, plus a comprehensive set of stimulus sequences for the protocols. Adoption of QVIP IP for the standard interfaces enabled Leonardo to focus on the unique specifics of the company’s design. QVIP and the UVM framework — a set of base classes layered on top of UVM — have enabled Leonardo to increase code coverage in a short period of time.

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