PCIe acceleration platform features Xilinx Versa AI IC

November 18, 2020 //By Rich Pell
Adaptive compute acceleration platform for PCIe
COTS FPGA solutions supplier Alpha Data has announced what it says is the first deployable adaptive computing acceleration platform (ACAP)-based data processing unit suitable for PCIe deployment.

Based around the Xilinx Versal AI Core series, the ADM-PA100 offers fully customizable IO and meets requirements for a range of markets including data center, machine learning, HPC, scientific instrumentation, and test and measurement. The Versal AI Core series includes an array of Xilinx AI engines (dedicated VLIW processors, capable of vector math processing at compute densities 5x higher than programmable logic), closely coupled with programmable logic allowing highly efficient implementation of custom coprocessing operations in this data flow.

The Xilinx Versal series of devices also feature an on-chip programmable network on chip (NoC) that improves on-chip programmable logic routing in large designs), dedicated hardened IP for multi-rate 100G Ethernet, hardened PCIe Gen4 endpoints with DMA outside the programmable logic, hardened DDR4 memory controllers, built in ARM A72 and R5F CPUs, and programmable logic and DSP performance a generation on from UltraScale+ devices, says the company.

Manuel Uhm, director of Silicon Marketing at Xilinx says, "The hardware adaptability and heterogeneous architecture of Versal AI Core ACAPs are a key advantage over traditional accelerators that typically focus on a subset of applications. This enables the creation of multiple domain specific architectures targeted to specific workloads. We're delighted that Alpha Data has chosen Versal AI Core series for its ADM-PA100 board to accelerate a breadth of workloads in cloud, networking, and edge markets."

The ADM-PA100 makes this programmable power available on a platform that can be deployed in PCIe format as a co-processor in an x86 CPU server system, or standalone using the ARM A72 for all the general-purpose processing requirements. IO flexibility is one key advantage of ACAP and FPGA over other classes of devices, says the company, allowing data to be processed directly with minimal latency and maximum bandwidth. The ADM-PA100 supports this IO flexibility with a front facing FMC+ socket supporting 24 Gigabit transceiver lanes and a full FMC HPC interface with 160 GPIO, which can interface with a

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