Packet header search and classification IP

June 09, 2020 //By Julien Happich
accelerator
MoSys’ Graph Memory Engine (GME) Accelerator IP is now running on Intel Stratix 10 FPGAs. The GME is part of MoSys’ Packet Classification Platform, which was announced earlier this year, and is capable of performing embedded search and classification of packet headers.

A typical use would be an alternative to TCAM functions. The proprietary platform software enables the compilation of TCAM images into graphs for GME processing. The GME product offering includes software, firmware and RTL and utilizes a common API and common RTL interface to facilitate platform portability.

Three implementations of GME will be available including: Pure hardware-agnostic, software version offering maximum flexibility and capacity; RTL-only version for use in an Intel FPGA for hardware-accelerated performance with no external MoSys memory device required; Maximum performance version when an FPGA is connected to a MoSys Programmable HyperSpeed Engine (PHE), with its 32 embedded 8 way threaded RISC cores.

Packet classification applications can now run much faster because the search performance on an FPGA when combined with a MoSys PHE can result in up to 100x performance improvement over a software solution running on a single core of CPU with DRAM. An implementation that uses the MoSys PHE provides enough additional performance to support the search throughput needed for two 100G ethernet ports.

Target applications include FPGA-based SmartNICs and acceleration cards in a broad range of markets.

MoSys - www.mosys.com


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