OpenHW ecosystem implements Imperas RISC-V reference models: Page 2 of 2

July 22, 2020 //By Ally Winning
Imperas Software has announced that OpenHW Group has established the CORE-V processor verification test bench using the Imperas RISC-V reference model.
Imperas Software has announced that OpenHW Group has established the CORE-V processor verification test bench using the Imperas RISC-V reference model.
testbenches is SystemVerilog,” said Steve Richmond, Verification Manager at Silicon Laboratories Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.”

“The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution,” said Jingliang (Leo) Wang, Principal Engineer/Lead CPU Design Verification at Futurewei Technologies, Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.”

“As the momentum builds around open source hardware, the OpenHW Group is providing a forum for leading commercial firms to collaborate on the verification of RISC-V processor IP cores,” said Simon Davidmann, CEO at Imperas Software Ltd. “With focused resources and expert methods, the collective group effort is set to achieve tape-out quality for open source cores with full transparency on the methods, test benches and results for state-of-the-art RISC-V processor verification.”

Availability
Imperas’ SystemVerilog testbench framework is maintained as part of the OVPworld.org library of example platforms. The library of processor models and example platforms are available at www.OVPworld.org, which is a community-based approach that allows users, customers and partners to share and collaborate on projects.

More information

www.OVPworld.org/openhw

www.imperas.com

Design and test plan

https://core-v-docs-verif-strat.readthedocs.io/en/latest/

https://github.com/openhwgroup/core-v-verif

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