The implementation will deliver quality IP cores to the OpenHW Group ecosystem and the open source hardware community.
Processor verification has 4 key parts (1) a DV plan, (2) the tests to run, (3) a device-under-test (DUT) to test, and (4) a reference model for comparison with discrepancy debug and resolution.
In the DV stage of verification, metrics are used to monitor and record the overall progress, as well as to ensure a smooth conclusion. Key steps in the process are the routine analysis and resolution steps, which identify and resolve faults. Full and complete accounting as all the steps are completed gives the DV team confidence to continue to collaborate and complete the tasks efficiently.
Random instruction stream generators are a commonly used processor DV technique that is used to test the complex states and extreme corner cases. The popular Google open source project, RISCV-DV ISG is a example of such a test source. It can be found on GitHub at https://github.com/google/riscv-dv. Setting up the SystemVerilog test environment to run the tests in a side-by-side configuration, with the DUT and reference model, provides a step-and-compare methodology that avoids the inefficiencies of logfile based methods and supports direct analysis of any issues found. As a processor has a complex state-space, a step-and-compare approach also supports advanced techniques with dynamic testbenches using UVM (Universal Verification Methodology) and SystemVerilog stimulus/response features.
“The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption,” said Rick O’Connor, Founder and CEO at OpenHW Group. “Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.”
“Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for