The IP core comes with a fully working reference design including Sensor to Image’s MVDK and IMX274 MIPI FMC module. The MVDK reference design is for a Zynq Ultrascale+ FPGA. The physical interface is abstracted by the Xilinx D-PHY core, making it simple to port to other FPGA platforms, such as 7 series Xilinx FPGAs.
The MIPI CSI-2 Receiver IP Core is delivered as encrypted VHDL with VHDL source code as an option. It is compatible with Xilinx Artix7, Kintex7, Zynq7 and Ultrascale+ FPGAs. The software library is delivered as an object file, with an option for C source code.