New MIPI CSI-2 receiver IP core for Xilinx FPGAs

October 06, 2019 //By Ally Winning
Sensor to Image’s new MIPI CSI-2 Receiver IP core is intended to provide a solution for decoding video streams from CSI-2 sensors in a Xilinx FPGA.
Sensor to Image’s new MIPI CSI-2 Receiver IP core is intended to provide a solution for decoding video streams from CSI-2 sensors in a Xilinx FPGA.

The IP core comes with a fully working reference design including Sensor to Image’s MVDK and IMX274 MIPI FMC module. The MVDK reference design is for a Zynq Ultrascale+ FPGA. The physical interface is abstracted by the Xilinx D-PHY core, making it simple to port to other FPGA platforms, such as 7 series Xilinx FPGAs.

The MIPI CSI-2 Receiver IP Core is delivered as encrypted VHDL with VHDL source code as an option. It is compatible with Xilinx Artix7, Kintex7, Zynq7 and Ultrascale+ FPGAs. The software library is delivered as an object file, with an option for C source code.

More information

https://www.euresys.com/en/Products/IP-Cores/Sensor-IP-Cores/MIPI-CSI-2-Receiver-IP-Core

Related news

New FPGA provides hardware root-of-trust capabilities

Lattice Diamond for Road Vehicles Functional Safety Certified to ISO 26262

Omnitek releases a 3D LUT for colour space conversions

Flex Logix now licensing neural network acceleration core


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.