The new lines cut the amount of embedded Flash to the minimum, but still allow secure boot, sensitive code and real-time routines to run safely on-chip, leveraging access times over 25 times faster than for external Flash (for cache miss). If needed, applications can scale-up either by adding off-chip serial or parallel (up to 32-bit) memories and leveraging the MCUs’ broad external interfaces and eXecute in Place (XiP) capability, or by porting to other pin-to-pin compatible STM32F7 or STM32H7 MCU lines, with up to 2Mbyte Flash and up to 1Mbyte RAM, supported by the same ecosystem with the same easy-to-use tools.
The Value Lines still feature powerful STM32F7 and H7 features, such as peripherals, hardware accelerators, and the real-time architecture with ultra-fast internal buses, short interrupt latency, and fast (~1ms) boot-up. The MCUs are also energy efficient, with flexible power modes, gated power domains, and on-chip power management that simplify design and reduce BOM cost.
The entry-level STM32F730 delivers 1082 CoreMark performance running at 216MHz aided by ST’s ART Accelerator for zero-wait-state execution from Flash. Features include cryptographic hardware acceleration, a USB 2.0 High Speed port with PHY, and a CAN interface. There is a 64Kbyte Flash, 8KByte Instruction and data caches for high-performance execution from internal or external memories, 256KB of system RAM and 16kB+64KB of Tightly Coupled Memory (TCM) for the most critical routines and data.
The STM32F750 adds a TFT-LCD controller with ST’s Chrom-ART Graphics Accelerator. It has hardware acceleration for hash algorithms, two CAN interfaces, an Ethernet MAC, camera interface, and two USB 2.0 interfaces with Full Speed PHY. There are 64Kbytes of Flash, 4Kbyte instruction and 4Kbyte data caches, 320KB of system RAM, and 16kB+64KB TCM.
The high-end STM32H750 delivers 2020 CoreMark performance at 400MHz and adds a hardware JPEG coder/decoder to the TFT controller and Chrom-ART Accelerator for faster GUI performance. There is also a CANFD port and additional CANFD with time-trigger capability and