New core and tools make implementing RISC-V quicker

December 06, 2018 // By Ally Winning
Codasip has launched the latest version of the company's Studio tool and the Bk7 RISC-V core, which has been optimised for Linux and real-time performance.

Studio allows a high-level description of a processor to be written in CodAL and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK (C/C++ compiler, debugger, profiler, etc.). Development time is reduced due to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

The 8 th generation of Codasip Studio adds significant new functionality and features. Specifically, Studio 8 includes:

• Support for LLVM debugger (LLDB) and OpenOCD,

• LLVM 7.0,

• Studio/CodeSpace IDEs based on Eclipse Oxygen along with more interactive consoles,

• improved test suites and verification to better support user-defined RISC-V extensions.

Studio has also been used to develop the Bk7 processor, the latest RISC-V micro-architecture in the Codasip portfolio. Bk7 is a 64-bit machine with a balanced 7-stage pipeline with branch prediction, optional full MMU with virtual addressing support for operating systems such as Linux, and support for popular RISC-V standard extensions and industry-standard external interfaces. Bk7 is Codasip’s highest-performance processor to date and is fully customisable, so additional instructions, registers or interfaces can easily be implemented.

Bk7 comes with the following deliverables:

• Readable Verilog or VHDL RTL along with test benches and synthesis scripts,

• SDK consisting of LLVM-based compiler, advanced profiling and debugging tools,

• both cycle-accurate and fast instruction-accurate simulation tools.

Studio 8 and the Bk7 processor are generally available in the first quarter of 2019, with early access to selected customers immediately.

More information

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