Up to now, hardware accelerators for machine learning have been built primarily with GPUs and FPGAs. According to eSilicon, the machine learning ASIC platform (MLAP) segment of the market has been under-served due to the dynamic nature of AI/machine learning algorithms. These algorithms typically experience a high degree of change as they are adapted to the end application, making it problematic to use a static, full-custom ASIC platform.
Through customized, targeted IP offered in 7nm FinFET technology and a modular design methodology, the neuASIC platform is said to remove the restrictions imposed by changing AI algorithms. The platform includes a library of AI-targeted functions that can be quickly combined and configured to create custom AI algorithm accelerators. With the use of a Design Profiler and AI Engine Explorer, eSilicon-developed and third-party IP can be configured as AI “tiles” via an ASIC Chassis Builder, allowing early power, performance and area (PPA) analysis of various candidate architectures. The neuASIC platform also uses a sophisticated knowledge base to ensure optimal PPA.
The elements of neuASIC IP library include functions that are found in most AI designs, resulting in a core architecture that is both optimized and durable with respect to AI algorithm changes. Specific algorithm modifications can be accommodated through a combination of minor chip revisions that integrate appropriate AI “tiles” or modifications of the 2.5D package to integrate appropriate memory components.