The work, which was supported by Analog Devices Inc., the National Science Foundation, and the Air Force Research Laboratory, was reported in Nature.
Carbon is being investigated as the active material in leading-edge transistors as it offers a faster alternative but one advantage of the research demonstrator made at MIT is that beyond the specialized carbon nanotube FETs (CNFETs) the development used standard commercial design tools and manufacturing infrastructure.
Silicon transistors have served the electronics industry well for many decades but scaling of the speed and physical size of these transistors has become increasingly complex and expensive; driving research into alternative materials and physical orientations.
Research indicates CNFETs could offer 10x the energy efficiency and 3x higher speeds than silicon but defects introduced during the, as yet, unscaled manufacturing process has hindered adoption.
MIT's major contribution is to have invented techniques fabricate that limit defects and enable controllable complementary CNFETs to be made and which can then be used as surrogates for CMOS manufacturing in conventional design flow.
The team used platinum or titanium metal contacts to define the transistors as P- or N-type and then coated them in an oxide compound them to tune the transistors for performance or power consumption.
MIT's solutions include RINSE (removal of incubated nanotubes through selective exfoliation), MIXED (metal interface engineering crossed with electrostatic doping) and DREAM (designing resiliency against metallic CNTs).
The Nature paper describes the microprocessor design and includes more than 70 pages detailing the manufacturing methodology.
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