LPDDR4/4X memory IP subsystem achieves ISO 26262 ASIL C

April 19, 2019 //By Ally Winning
LPDDR4/4X memory IP subsystem achieves ISO 26262 ASIL C
The Cadence LPDDR4/4X memory IP subsystem using TSMC’s 16nm FinFET Compact (16FFC) process, has achieved ISO 26262 ASIL C certification.

The certification was granted by SGS-TÜV Saar and confirms that the Cadence IP is ready for use when creating advanced SoCs for ADAS and L3/L4 autonomous driving applications. The Cadence LPDDR4/4X memory subsystem includes the Cadence 4266 speed grade LPDDR4/4X DDR PHY, controller IP, and Cadence VIP.

More information

www.cadence.com/go/lpddr4ipac

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