PSoC 6 MCU architecture is built on an ultra-low-power 40nm process technology, with dual-core Arm Cortex-M4 and Cortex-M0+ processors. The dual processor configuration allows developers to optimise designs for performance and power consumption. The MCUs also offer easy-to-use software-defined peripherals and the integrated security features. The PsoC 6 family has up to 1MB Flash and 288KB SRAM, Bluetooth Low Energy 5.0 connectivity, and Cypress’ CapSense capacitive-sensing technology.
Security is provided by the architecture’s hardware-based Trusted Execution Environment (TEE) with secure boot capability and data storage for the protection of firmware, applications and other secure assets. The MCUs also feature a variety of industry-standard cryptographic algorithms, including ECC, AES and SHA 1,2,3, all within an integrated hardware coprocessor.
Other features of the family include PDM-PCM interface and Quad-SPI interfaces; full-speed USB connectivity; plus nine serial-communication blocks, seven programmable analogue blocks and 56 programmable digital blocks.
Accompanying development kits will also be sold by RS. These include:
- PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WIFI-BT) - a low-cost hardware platform that enables design and debug of the PSoC 62 MCU and the Murata LBEE5KL1DX module.
- CY8CKIT-062-BLE PSoC 6 Pioneer Kit for the IoT - a general-purpose PSoC 6 kit with the PSoC 63 MCU w/ BLE 5.0 compliance.
- Clicker 2 for PSoC 6 Development Board - which contains a PSoC 63 MCU w/ BLE 5.0 compliance and simplifies interfacing with the Click platform.
Hall C5, Stand 147