Low jitter clocks target communications and data centers

April 28, 2021 // By Jean-Pierre Joosting
Low jitter clocks target communications and data centers
Family of ultra-low jitter clock generators and jitter attenuators simplifies design with industry’s lowest power and smallest 75 fs jitter clocks.

Renesas Electronics Corporation has expanded its timing portfolio with a new sub-100-fs point-of-use clock for data center, server, and network infrastructure markets. The latest FemtoClock2 family includes ultra-low jitter clock generators and jitter attenuators in a small 4x4 mm2 package, enabling cost-effective and simple clock tree implementation for next-generation, high-speed interconnect designs.

Featuring best-in-class jitter as low as 64 fs RMS, FemtoClock2 enables customers to easily meet next-generation PAM4 requirements on new switch or router designs. With a 4x4 mm2 form factor, the FemtoClock2 family is less than one third the size of similar products on the market. This allows designers to place the clock source at the point of use – very close to the device receiving the clock signal – for streamlined PCB layout design, reduced cross talk, and cleaner signals. Flexibility makes the family useful in many applications. FemtoClock2 can be configured as a DCO, clock generator, or jitter attenuator, offering valuable design flexibility and reuse.

“PAM4 technology is enabling a major leap in data transmission rates in both communications and data center segments resulting in stringent requirement on the clock in such systems,” said Bobby Matinpour, Vice President of Timing Products, Data Center Business Division at Renesas. “Expanding our popular FemtoClock lineup, Renesas offers a new high-performance family that delivers superior jitter performance with low power in a small form factor, enabling placement of the clock anywhere on the board at the point of use. This greatly simplifies the design by eliminating the additive jitter associated with the extensive clock routing on the board.”


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