IP blocks build custom FPGA-hosted algorithms to speed data acceleration

October 18, 2017 // By Graham Prophet
IP blocks build custom FPGA-hosted algorithms to speed data acceleration
Achronix’ Speedcore custom IP blocks, for implementation on its eFPGA devices, promise greatly improved performance, power, and area; and,the company says, enable functionality that has never before been possible in standalone FPGAs. Custom blocks can result in as much as a 90% reduction in the die area required for a given function.

Achronix Speedcore eFPGAs accelerate data-intensive AI / machine learning, 5G wireless, automotive ADAS, datacentre and networking applications, achieving ASIC efficiency while retaining FPGA flexibility. This results in a highly efficient implementation that minimises power and area while maximising data throughput.

 

Speedcore itself is also IP; the ‘base’ IP creates embedded FPGA (eFPGA) that can be integrated into an ASIC or SoC. Customers specify their logic, RAM and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Speedcore look-up-tables (LUTs), RAM blocks, DSP64 blocks and custom blocks can be assembled in flexible columns to create the optimal programmable function for any given application. The custom IP blocks are a further layer that configures the FPGA fabric for specific tasks.

 

Traditional CPU-based architectures, Achronix comments, are not scaling to meet the exponential growth in compute demand that is required by the new wave of intelligent data-intensive applications. This is driving the need for new, heterogeneous compute architectures with programmable hardware accelerators. Speedcore eFPGAs can deliver performance and lowest-cost hardware acceleration; functions that traditionally ran slowly and consumed significant resources in standalone FPGA fabrics are optimised for maximum performance and minimal die area as illustrated in the following examples.

 

- The area of a CNN-based YOLO object recognition algorithm was reduced by over 40% by optimising the DSP and memory blocks for matrix multiplication.

- Large string search functions that require parallel comparator arrays resulted in area reduction of over 90% when implemented in Speedcore custom blocks.

- Barrel shifters and bit manipulation structures can be fully implemented in Speedcore custom blocks allowing larger, sophisticated applications in the same area and increasing achievable frequency.

- The core functionality of a 400 Gbps packet processing data-path running at 800 MHz is implemented in Speedcore custom blocks with the programmable logic managing the analysis and control functionality. Today’s standalone FPGAs cannot support this high throughput for packet processing applications.

 

Steve Mensor, Vice President of Marketing, Achronix Semiconductor comments, “The companies that we are working with are building the next generation of heterogeneous compute platforms and high-bandwidth communication systems. They are building high-performance hardware accelerators that can be changed over time as their compute algorithms evolve. Achronix eFPGA IP, now with Speedcore custom blocks, allows them to have programmability with ASIC-level performance and die-size efficiency.”

 

Speedcore custom blocks are defined collaboratively by Achronix with its customers through a detailed architecture analysis of acceleration workloads. Repeated functions that are performance and/or area bottlenecks are evaluated as candidates to be hardened into Speedcore custom blocks. A new release of ACE design tools that includes the new Speedcore eFPGA with custom blocks is then provided to customers for benchmarking and evaluation. If required, the process is iterated to create the optimal solution for the customer’s system.

 

Achronix ACE design tools fully support Speedcore custom blocks from design capture to bitstream generation and system debug in the same way as memories and DSP blocks. Achronix creates a unique GUI for each Speedcore custom block that manages all configuration rules. ACE contains full timing details for all configurations of the Speedcore custom blocks, which allows ACE to complete timing-based place-and-route for designs. Customers can use the Floorplanner tool for design optimisation, and to make regional or site assignments for all block instances. ACE also includes a critical path analysis tool that allows customers to analyse timing. Customers can also use ACE’s powerful SnapShot embedded logic analyser to create complex triggers and show run-time signals within Speedcore.

 

Achronix Semiconductor; www.achronix.com

 

 

 


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