With its high-performing hexa-core architecture and its features for connectivity, security and embedded safety, the AURIX family TC3xx is intended for a wide field of automotive applications. In addition to engine management and transmission control, powertrain applications include new systems in electrical and hybrid drives. Specifically, hybrid domain control, inverter control, battery management, and DC-DC converters will benefit from the new architecture. The AURIX TC3xx microcontrollers are also suited, Infineon says, to safety-critical applications ranging from airbag, braking and power steering to sensor-based systems using radar or camera technologies. The combination of performance and a powerful safety architecture suits the TC3xx family for domain control and data fusion applications supporting the next levels towards automated driving.
The AURIX TC3xx family will be highly scalable and offer Flash memory sizes of up to 16 MByte and more than 6 MByte of integrated RAM. Compared to today’s AURIX TC2xx microcontrollers with up to three TriCore cores, the TC3xx multicore architecture provides up to six TriCore cores, each with a full clock frequency of 300 MHz. Four of the six cores feature an additional lockstep core enabling a new level of ISO 26262 functional safe computational power on a single integrated device: Up to 2400 DMIPS performance supporting applications classified ASIL-D, compared to up to 740 DMIPS with the previous AURIX architecture.
The performance increase and the reuse of existing safety concepts allow automotive system suppliers to reduce development costs and cut time-to-market. More functions can now be implemented on a single microcontroller, such as powertrain and chassis domain control and next generation radar and fusion algorithms.
Automotive radar systems ranging from blindspot monitoring to advanced front radar specifically benefit from the capabilities of the AURIX TC3xx family. TC3xx microcontrollers will feature a radar processing sub-system with up to two dedicated Signal Processing Units running at 300 MHz enabling computation of next-generation radar algorithms on a single chip. In addition,