Imperas expands free riscvOVPsimPlus RISC-V simulator

December 07, 2020 // By Ally Winning
Imperas Software has updated and extended the Free riscvOVPsimPlus RISC-V reference model and simulator with additional features.
Imperas Software has updated and extended the Free riscvOVPsimPlus RISC-V reference model and simulator with additional features.

The new features include full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options.

Imperas has also included full standard CLIC features, Debug Module / Mode, Hypervisor “H” simulation, and also 'near-ratified' ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions in the updated model.

riscvOVPsimPlus is an Instruction Accurate RISC-V processor simulator (ISS) that has been based on Imperas Open Virtual Platform (OVP) technology with Just-in-Time Code Morphing simulation technology, which executes RISC-V code on a Linux or Windows x86 based host computer. The riscvOVPsimPlus simulator is flexible, accurate, and fast, with a performance of over 2,000 MIPS on a modestly configured host machine. It can be used as a platform target to develop bare metal, OS Ports (Linux or RTOS), drivers or full application software.

The free riscvOVPsimPlus simulator has been designed to help RISC-V adopters to become compliant with the RISC-V specifications. Imperas RISC-V reference models and simulation technology has been used within RISC-V International’s compliance test suite since 2018, and also in verification working groups within CHIPS Alliance and the OpenHW Group.

“Software and hardware co-design is essential for modern domain-specific devices in applications such as AI and Machine Learning,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the new riscvOVPsimPlus offering, we are enabling adopters to explore the full envelope of the RISC-V Specifications with support for both for early software development and hardware verification. The RISC-V ISA Specification defines the hardware-software boundary and designers can start innovating now by adopting the free Imperas riscvOVPsimPlus.”

riscvOVPsimPlus was developed to offer the configurablity to represent the same implementation choices that RISC-V processor implementors choose. This ability makes it an excellent tool for designing and testing RISC-V application software and verification and architectural validation/compliance test suites.

The simulator can connect to GDB and Eclipse for source code debug and can be run in batch mode for regression testing and use in continuous integration environments. It also has many trace options to assist in program development. riscvOVPsimPlus has built-in instruction functional coverage measurement and reporting to assess both test quality and progress in test plan metrics.

More information

www.ovpworld.org/riscvOVPsimPlus

https://www.imperas.com/articles/imperas-3rd-annual-risc-v-summit-december-8-10-2020

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