Imec shows optimized process flows for Ge-based devices

June 12, 2019 //By Ally Winning
Image 1: Improved performance and reliability of the Ge nFinFET device. (Left:)
imec will report improved performance for Ge-based n-type FinFETs and Ge-based p-type gate-all-around (GAA) devices at the 2019 Symposia on VLSI Technology and Circuits.

For Ge n-type FinFETs, pre-gate stack process optimization improved reliability and performance. Tests show 100% improvement in positive bias temperature instability (PBTI) and improvement in GmSAT vs. SSSAT benchmark. For Ge-based p-type GAA device, excellent short-channel control and performance were achieved with an improved extension-less junction scheme. Together, these results confirm the potential of Ge-based CMOS transistors as high-performance solutions for the 3nm and beyond technology nodes.

Ge boasts higher intrinsic mobility in comparison to Si, and Ge-based FinFET devices have the potential to be a non-disruptive performance booster for future technology nodes. While Ge p-type FinFET devices have been extensively studied, the development of well-performing, reliable Ge n-type FinFET devices is lagging behind. Imec’s proposed for an optimized process flow for the gate stack solves one of the major challenges for Ge n-type FinFET development.

Key to the successful gate stack formation is an improved pre-cleaning and an optimized dummy gate oxide deposition and removal process, as part of a replacement metal-gate (RMG) process flow. Imec’s optimized process flow resulted in 100% improved positive bias temperature instability (PBTI) and a 100% improvement in GmSAT vs. SSSAT benchmark.

In the organization’s second paper, imec will propose a scheme for achieving good short channel control while preserving transistor performance in p-type strained Ge-based GAA devices. An improvement in short channel control that allows gate length scaling down to 25nm was achieved by using an extension-less scheme - without dopant implantation in the ‘extension’ region next to the gate. To maintain the transistor’s performance, the extension-less scheme was combined with spacer thickness reduction, and with the implementation of highly boron-doped Ge or GeSn as source/drain material. The optimized process flow resulted in a 55% improvement in GmSAT Vs. SSSAT benchmark on Ge GAA devices as compared to previous work. Short channel (LG~25nm) device also shown excellent Gm (Gm,lin=512µS/µm, Gm,sat=2220µS/µm).

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