GENIO's holistic design environment dramatically shortens design cycle time through unique features that include cross-hierarchical, 3D-aware, design methodologies that streamline the entire IC eco-system. It has proven to be very application and packaging friendly, featuring quick IC, package, system constraints definition/import/export and a seamless interface with existing EDA environment and custom design flows.
The result is right-the-first-time concept-to-design methodology, thanks to strong "what-if" analysis and system level exploration across architectures. GENIO™ identifies the most proficient solution and avoids entering "dead-end" architectures/design roads. At the same time, it automates and optimize hundreds of thousands of connections, minimizing the number of physical resources needed for system interconnect.
GENIO™ also eliminates design environment boundaries to enable system architectural exploration that identifies errors and bottleneck early in the design process. It also features cross-hierarchical pathfinding for pin assignment optimization, wire lengths/crossovers reduction, and floor planning-aware silicon interposer design.
Further reading
The acceleration of design automation to the cloud in 2020
RTL simulation acceleration for Microchip FPGAs
Chip verification industry could benefit from software techniques
