IAR Systems support for the RISC-V P extension

June 05, 2020 //By Ally Winning
IAR Systems support for the RISC-V P extension
IAR Systems has announced initial support for the draft RISC-V P extension in the company’s IAR Embedded Workbench for RISC-V development tools.

The early support for the Andes Technology implemented extension, a Premier Founding member of RISC-V International, will allow developers to take advantage of the toolchain for applications based on the new RISC-V core extension.

RISC-V International currently standardizing a series of standard extensions, beyond the integer base instructions, which can be used or left out according to the design goals. The RISC-V P extension has been developed as a standard extension for Packed-SIMD instructions. The extension allows efficient media processing for audio, voice and images, and is a generalization of a Packed-SIMD extension donated to the RISC-V International by Andes Technology Corporation.

“We have achieved around 9x performance boost of CIFAR-10 inference with RISC-V P extensions. Packed-SIMD provides edge processors more computing power with higher energy efficiency and minimal increase in cost, and such capability empowers edge devices to deal with voice and slow video processing,” comments Dr. Chuanhua Chang, the Chair of RISC-V P extension Task Group and Head of Architecture Division of Andes Technology Corporation. “The partnership with IAR Systems will further accelerate the performance of applications based on RISC-V in general and P extension in particular.”

The free and open RISC-V ISA is based on established RISC principles. IAR Embedded Workbench for RISC-V offers excellent optimization technology, ensuring the application fits the required needs and optimizes on-board memory use. To ensure code quality, the toolchain includes C-STAT for integrated static code analysis. C-STAT can help prove compliance with specific standards like MISRA C:2004, MISRA C++:2008 and MISRA C:2012, as well as detect defects, bugs, and security vulnerabilities as defined by the Common Weakness Enumeration (CWE) and a subset of CERT C/C++.

The current version of IAR Embedded Workbench for RISC-V provides support for RV32 and RV32E 32-bit RISC-V cores and extensions. Future releases will include 64-bit support, as well as functional safety certification and security solutions.

More information

www.iar.com/riscv

Related news

IAR DevCon dates scheduled for Europe


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.