Typically, such devices are made of barium titanate or hafnium dioxide but display poor tunnelling electroresistance and have a barrier height modulation of around 0.1eV.
The USC team report on a device made with layered copper indium thiophosphate (CuInP2S6) as the ferroelectric barrier, and graphene and chromium as asymmetric contacts. The material can induce a barrier height modulation of 1eV in the junction, which results in a TER of above 10^7.
The device offers promise for integration with silicon-based electronics.
"These materials allow us to build devices that can potentially be scaled to atomic-scale thickness," said Han Wang, associate professor of electrical and computer engineering at USC. "This means the voltage required to read, write, and erase data can be drastically reduced which in turn can make the memory electronics much more energy efficient."
The memory has wide scope for applicability from flash memory replacement as discrete memory to DRAM replacement. The device has robust endurance and retention, the authors claim and could be engineered for applications in in-memory computing and other computing hardware.
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