EnSilica/BaySand tie-up offers configurable IP on multi-project wafers

August 18, 2016 //By Graham Prophet
EnSilica/BaySand tie-up offers configurable IP on multi-project wafers
ASIC designers who are working with BaySand’s metal-programmable ASIC technology can, through an agreement between the companies, access EnSilica’s configurable eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware accelerators.

IP provider EnSilica (Wokingham, UK) has teamed with BaySand, supplier of application configurable ASICs, to provide customers of BaySand’s ASIC UltraShuttle-65 multi-project wafer (MPW) with a range of IP solutions that can be configured to their specific application requirements.


EnSilica’s automated flow claims to deliver complex CPU sub-systems in a matter of days. This sub-system can include single or multiple eSi-RISC processor cores with JTAG debug, and a range of peripherals and timers as well as encryption accelerator cores to enable secure boot and communication. The system is built around standard multi-layer AMBA AHB bus fabric generated as part of the automated flow. Additional APB, AHB, AXI buses can be included to allow the integration of the customer’s own IP cores. This design flow potentially allows EnSilica processor sub-systems to be delivered to customers well ahead of the first ASIC UltraShuttle-65 MPW run in October 2016.


According to Ian Lankshear, CEO of EnSilica, “By supporting multiple projects customizable by four metal layers and facilitating access to deep sub-micron silicon by offering an affordable and reliable ASIC solution, the ASIC UltraShuttle-65 program redefines the traditional silicon shuttle concept offered by other foundries.”


With the support of a proven design flow and methodology that does not require any special EDA tools, expertise or licenses, the ASIC UltraShuttle-65 MPW program is structured to deliver high quality, verified and fully tested ASICs. The methodology is based on BaySand’s fully characterized standard cell library, coupled with EnSilica’s eSi-family of silicon proven IP and combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation. The ASIC UltraShuttle-65 MPW can also be used for FPGA to ASIC conversion minimizing risk, reducing the cost and shortening the time-to-market.


EnSilica’s eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scale across a wide

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