Early-access program for RISC-V enabled PolarFire SoC family

December 11, 2019 //By Ally Winning
Microchip has announced further details on its RISC-V enabled PolarFire SoC FPGA family, and also opened an Early Access Programme (EAP) for devices.
Microchip has announced further details on its RISC-V enabled PolarFire SoC FPGA family, and also opened an Early Access Programme (EAP) for devices.

The platform integrates a hardened real-time, Linux capable, RISC-V-based MPU subsystem on the mid-range PolarFire FPGA family, bringing low power consumption, thermal efficiency and defence grade security to embedded systems.

Microchip’s Libero SoC 12.3 FPGA design suite and SoftConsole 6.2 IDE can be used by qualified early access to start designs and Renode for debug.

PolarFire SoC uses up to 50 percent less power than competitive devices. It is the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux plus real-time applications.

PolarFire ecosystem partners ready to support PolarFire SoCs include WindRiver, Mentor Graphics, WolfSSL, ExpressLogic, Veridify, Hex-Five, and FreeRTOS. IAR systems and AdaCore will also supply tools for the devices.

PolarFire SoC includes debug capabilities including instruction trace and passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors from Mi-V partner UltraSoC, 50 breakpoints, FPGA fabric monitors, and Microchip's built-in two-channel logic analyser SmartDebug. The PolarFire SoC architecture includes reliability and security features such as Single Error Correction and Double Error Detection (SEC-DED) on all memories, physical memory protection, a Differential Power Analysis (DPA) resistant crypto core, defence-grade secure boot and 128 Kb of flash boot memory.

More information

www.microchip.com

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