The demonstration will initially be held at the FACE & SOSA technical interchange meeting and exposition in Dayton, Ohio.
INTEGRITY-178 tuMP conforms to FACE Technical Standard edition 3.0 and has the capability to execute a DO-178C Level A, B, or C application across multiple processor cores as defined in ARINC 653 Part 1, Supplement 4, Section 2 – “Multiple ARINC 653 processes within a partition scheduled to execute concurrently on different processor cores” (i.e. BMP). INTEGRITY-178 tuMP is also the only RTOS that meets the optional SMP requirement defined in ARINC 653, Part 2, Supplement 3.
INTEGRITY-178 tuMP features a fully capable multicore scheduler, as well as bandwidth allocation and management capability, called BAM. BAM controls and monitors shared processor resource access. The supported bandwidth management technique emulates a high-rate hardware-based approach to ensure continuous allocation enforcement. These capabilities lower integration and certification risk, while also enabling the integrator to manage significant software retest costs that would occur when a software application changes or is added.