German RISC-V core designer Codasip has opened a strategic design centre in France for its processor cores based on teh open source RISC_V instruction set architecture (ISA).
The centre in Villeneuve Loubet is near Sophia Antipolis where major technology companies such as Bosch, NXP, Thales, and many others have offices.
“As we are expanding the product portfolio and fostering our technology leadership, we need talented senior engineers to support the growth,” said Karel Masařík, CEO of Codasip. “Sophia Antipolis is an important European location for R&D and technical talent in the semiconductor industry. We are proud to have hired our French colleagues there, close to customers. Their expertise will be a great supplement to that of our main R&D Centre in the Czech Republic.”
The French team is currently focused mainly on product architecture and verification. The team’s leader is Mélaine Facon, an industry professional with rich experience in the semiconductor IP design field who was previously programme manager at ARM's site at Sophia-Antipolis.
“The RISC-V open ISA is revolutionizing the deployment of processors in SoCs by being a neutral standard independent of any single company,” said Facon as Director of the French Design Centre. “We are confident that our team’s experience can help respond to the rapidly increasing demand for RISC-V processors, and we are really looking forward to becoming a part of Codasip and its RISC-V story.”
Codasip is a founding member of the RISC-V Foundation and a long-time supplier of LLVM and GNU‑based processor solutions and currently has offices in Europe and China.
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