Cadence Design Systems and United Microelectronics Corporation have announced that the Cadence digital full flow has been optimized and certified for the UMC 22ULP/ULL process technologies to accelerate consumer, 5G and automotive application design. The flow, which incorporates leading implementation and signoff technology for ultra-low-power designs, enables mutual customers to deliver top-quality designs and achieve a faster path to tapeout.
The Cadence digital full flow that has been optimized for use on UMC’s 22ULP/ULL process technologies includes the Innovus™ Implementation System, Genus™ Synthesis, Liberate™ Characterization, Quantus™ Extraction, Tempus™ Timing Signoff, Litho Physical Analyzer and Physical Verification System.
Key capabilities that enable 22ULP/ULL design include:
- Best-in-class design implementation and optimization engines — The engines are fully integrated from RTL to GDSII, enabling users to achieve power, performance and area (PPA) goals and reduce time to market.
- Optimal signoff convergence — Cadence offers the only digital flow with fully integrated place-and-route, timing signoff, physical verification and IR drop/power signoff capabilities, which provide unparalleled last-mile design closure with the fewest iterations to facilitate the timely delivery of advanced-node products.
- Low-power standard cell library development and characterization — UMC replaced its incumbent library characterization tool with Cadence Liberate Characterization, which is the foundation of the broader digital full flow and a critical piece that enables advanced timing and power analysis, optimization and signoff flows.