Cadence adds 10 new Verification IP

May 21, 2020 //By Ally Winning
Cadence has announced 10 new Verification IP (VIP) solutions to quickly verify designs for customers developing SoCs and MCUs.
Cadence has announced 10 new Verification IP (VIP) solutions to quickly verify designs for customers developing SoCs and MCUs.

The additional VIP portfolio supports automotive, hyperscale data center and mobile applications, including for CXL, HBM3, TileLink and MIPI CSI 2sm 3.0.

Cadence VIP are part of the Cadence Verification Suite which supports the company’s Intelligent System Design strategy. Cadence Verification Suite features core engines and verification fabric technologies to increase the verification throughput and design quality.

The new Cadence VIP offers a consistent API across all VIP with complete bus functional models (BFMs), integrated protocol checks and coverage models. The new VIP solutions support multiple application areas and specifications, including:

• Hyperscale data center:
o CXL – Compute Express Link
o HBM3
o Ethernet 802.3ck

• Automotive:
o CSI-2 3.0
o MIPI I3C 1.1

• Consumer and mobile:
o TileLink
o eUSB2
o UFS 3.1
o MIPI SPMIsm
o MIPI RFFEsm v3.0

All Cadence VIP include Cadence TripleCheck technology to provide a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure interface specification compliance.
 

More information

www.cadence.com/go/NewVIP

Related news

Tensilica Vision DSP doubles vision and AI performance

Cadence releases functional verification IP for USB4

Cadence JasperGold helps Hitachi to comply with IEC 61508 Series SIL 4 requirements

Cadence and Nvidia partner to apply machine learning to EDA

 

 


Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.