Andes Technology announces its FreeStart program

June 12, 2019 //By Wisse Hettinga
Andes Technology announces its FreeStart program
AndesCore™ RISC-V CPU IP N22 integrated with interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform

The FreeStart program offers an easy and fast way to build a solid SoC foundation on the commercial-grade RISC-V CPU core N22, available for free download. AndesCore™ N22 is an entry-level, ultra-compact, low-power and performance-efficient RISC-V CPU IP. It delivers the highest 3.95 Coremark/MHz in its class, and offers rich configurable features, including multiplier, interrupt controller, local memory, instruction cache, debug support, and an optional AHB platform. With the RISC-V FreeStart program, SoC engineers can begin designing a RISC-V based SoC without budgeting CPU IP upfront.

The N22 CPU is a 2-stage pipeline 32-bit RV32I/EMAC RISC-V CPU core, 16 or 32 general purpose registers, multiplier, atomic and compressed instructions. It also supports several unique and configurable features such as StackSafe™ for hardware stack protection, PowerBrake for efficient power management, CoDense™ for code size reduction on top of RISC-V C extension, and local memory and instruction cache for performance boost. The FreeStart program also provides designers the option of 1-year support and a pre-integrated AHB platform with commonly used peripheral IPs, thus saving the time of sourcing and integrating these into their design. In addition, the RISC-V FreeStart can leverage the AndeSight™ IDE, a professional software development environment with over 15,000 worldwide installations, which has been available for free download.

The FreeStart also provides mass production program and university programs that allow industry and academy to make commercial chips with running royalty or for research purposes but allow path of migration to mass production.

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