Agile Analog, a supplier of highly configurable process node-agnostic analog IP building blocks, has been accepted as a strategic member by RISC-V International, the non-profit organisation which maintains RISC-V as a free and open processor instruction set architecture (ISA).
Increasing numbers of OEMs and manufacturers of SoCs and ASICs are choosing to base complex chip designs on the RISC-V architecture, as its open licence business model enables them to develop chip designs faster and to enjoy greater design flexibility than is possible when using proprietary processor architectures.
By joining RISC-V International as a strategic member, Agile Analog extends the RISC-V ecosystem to include a broad set of analog building blocks implemented in highly configurable IP. Demand is particularly strong in new RISC-V-based chip designs for security monitoring functions, such as clock glitch and voltage glitch detection, which are used to protect against side-channel attacks. Agile Analog’s configurable IP is also available to support a wide range of other analog functions including power management, sensing and signal processing.
The Agile Analog offering complements the open RISC-V ISA, as its analog IP can be configured to meet the functional requirements of each application, as well as the foundry, process and node in which the chip is to be fabricated. Just as chip designers have the freedom to optimise their implementation of the RISC-V ISA, Agile Analog also enables them to choose the configuration options for analog IP. The provision of application- and process-optimised analog IP is a unique capability of Agile Analog, and is in marked contrast to the existing business model for the supply of analog IP, which is limited to the provision of off-the-shelf, standard IP products.