The company performed a full range of bench and ATE tests across a full range of operating conditions to verify the Speedcore chip’s full functionality. Speedcore is a permutable architecture that can scale in size from ten thousand to two million look-up tables. The FPGA architecture fabric works in tandem with large amounts of embedded memory and DSP blocks.
The Speedcore eFPGA technology has been developed as IP to be embedded in SoCs and ASICs to bring reprogrammability to those devices. Achronix claims the eFPGA fabric takes up less die space, performs better, and has lower power and costs than a standalone FPGA. Achronox will configure look-up tables, memory and DSP resources to user specifications, so no resources are wasted.