In hall 3A, booth 235, the company will also demonstrate its Vitis unified software platform launched last year. The software is intended to introduce a wide range of new engineers to hardware adaptability.

Demos include:

Zynq Ultrascale+ Region of Interest (ROI) based encoding using Video Codec Unit (VCU)

This demonstration showcases ROI based encoding using the + Video Codec Unit (VCU). Vitis AI, allows the Xilinx Deep Learning Processor Unit (DPU) to be integrated in the pipeline to identify the ROI’s mask within the frame. Using the ROI’s mask information, VCU allocates more bits for ROIs in comparison to the rest of the region at a given bitrate to improve encoding efficiency.

Versal ACAP Machine Learning (ML) inference solution using Intelligent Engine (AIE) for edge use-cases

This demonstration introduces a ML inference solution for edge use cases on Versal ACAP. Using Xilinx tools, the system has been developed on a heterogeneous compute platform where adaptable engines integrate live video interfaces with pre/post-processing elements. Intelligent Engines (AIE) will implement ML inference compute-intensive algorithms and a scalar engine is used to run the OS to control the different elements within the pipeline.

Cloud-trained neural network on a connected Xilinx IIoT Edge device

Using Xilinx’ AWS certified boards, this demo highlights an easily accessible platform for collaboration between edge and cloud.

Real-time 3D calculation of physical effects using the Bullet Engine on Alveo accelerator boards

This demonstration shows the engine on a Xilinx Alveo accelerator board with smooth graphics output at high frame rate.

logiADAK7 Development Platform

Xylon’s logiADAK7 is the company’s latest ADAS development kit, based on the Xilinx Zynq Ultrascale+ MPSoC device. The logiADAK7 platform showcases multi-camera central module processing including the production-ready “ViewMore Natural Surround View” IP solution.

In addition to the demos on the stand, Xilinx will be presenting several topics including:

“Architecture Apocalypse: dream architecture for deep learning inference and compute -Versal AI Core” on Wednesday 26th February at 2pm

“Low-bit CNN implementation and optimization on FPGA” on Wednesday 26th February at 3pm

“Emerging SoC performance/power challenges and a dozen techniques” on Wednesday 26th February at 4pm

More information

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