Jitter Tutorial Part 2 of 2

By Silicon Laboratories
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As clock speeds and communication channels run at ever higher frequencies, engineers who have previously had little need to consider clock jitter and phase noise are finding that they need to increase their knowledge of these subjects. Part two of this jitter tutorial explores the phase-locked loop (PLL) characteristics that must be considered for PLL applications involving clock jitter, as well as the impact of clock buffers (fan-out buffers) on jitter. Read More

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