Webinar; Enabling functional safety for FPGA-based hardware design

Webinar; Enabling functional safety for FPGA-based hardware design

Technology News |
Synopsys has notified a forthcoming webinar which has the aim of showing how designers can automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.
By Graham Prophet

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The company expands in these terms; The need for functional safety integration for high-availability electronic systems that demand high uptime and high quality of service is growing in data centre, industrial automation and control, and medical applications. In space applications the incorporation of functional safety design techniques has been common for more than a decade, but with the advancement of FPGA process technologies and their use in terrestrial applications, even electronic equipment operating at sea level can experience “glitches” that can cause incorrect operation. Special design techniques are required to detect such faults and return the design to safe and correct operation.

 

The presentation will take place on June 28th, 2017, at 10am PDT (Pacific time); therefore, end-of-day for European viewers – 6pm BST or 19:00 CET. It is expected to last 60 minutes.

 

Topics covered will include:

Functional safety and requirements for hardware

How and when to use triple modular redundancy (TMR)

Techniques available to ensure safe operation of RAMs, Finite State Machines, Sequential logic, and design logic and the various considerations and trade-offs

How to constrain, visualize, and analyze your design using [Synopsys’] HDL Analyst functionality

Hardware design to help enable functional safety in system software

 

The speaker will be Paul Owens, Senior Technical Marketing Manager, Verification Group, Synopsys. Paul Owens is a senior Technical Marketing Manager within the Synplify Business Group at Synopsys. Paul has worked in Design Automation, CAE, ASIC and FPGA design and verification. He holds a BS in Electrical Engineering from U.C. Berkeley, and an MS in Computer Engineering from Santa Clara University.

 

Register here

 

 

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