Synopsys has announced the DesignWare® tRoot™ Hardware Secure Module (HSM) and ARC® SEM130FS Safety and Security Processor IP with integrated functional safety features to accelerate ISO 26262 certification of automotive systems-on-chips (SoCs).
The ASIL B compliant tRoot HSM for Automotive adds hardware safety mechanisms for protection against permanent, transient and latent faults to its security system that includes an ARC processor, scalable side-channel resistant cryptography, true random number generator and security-enabled external memory controllers. The ASIL D compliant ARC SEM130FS Processor adds safety-critical hardware features such as dual-core lockstep to meet stringent automotive safety requirements. Both the products are supported by comprehensive safety documentation, including failure modes, effects and diagnostic analysis (FMEDA) reports that facilitate chip- and system-level ISO 26262 ASIL B or ASIL D compliance.
“Security attacks on safety-critical ADAS, telematics, radar, V2X communications, and industrial systems are on the rise, and designers need to find ways to implement advanced security while eliminating points of failure,” said Wolfgang Ruf, product manager, semiconductors at SGS-TÜV Saar GmbH. “By extending its DesignWare tRoot HSM and ARC SEM Processor IP to include functional safety mechanisms, Synopsys is enabling designers to more easily deliver SoCs that meet their customers’ ASIL requirements and secure high-value data and communication from attacks.”
The Synopsys DesignWare tRoot HSM with Root of Trust provides designers with a trusted execution environment (TEE) as part of a pre-integrated, pre-verified safety and security solution. The tRoot HSM for Automotive also incorporates safety mechanisms such as hardware redundancy, register error detection codes (EDC), memory error correction codes (ECC), watchdog timers and self-checking comparators for the entire system. In addition, the tRoot HSM for Automotive protects sensitive information and data processing in the connected car with features including secure boot, debug, firmware updates and key management.
The Synopsys DesignWare ARC SEM130FS Processor with Synopsys SecureShield™ technology helps designers to protect safety-critical systems against software, hardware and side-channel attacks with ASIL D compliance covering both random hardware faults and systematic development flow. The processor offers integrated hardware safety features including dual-core lockstep, ECC for memories and interfaces, transient fault protection for internal registers, diagnostic error injection and an integrated self-checking safety monitor. The SEM130FS processor is supported by the certified ASIL D compliant ARC MetaWare Development Toolkit for Safety to ease the development, debugging and optimization of ISO 26262-compliant software. To help designers reach target ASILs, ARC FMEDA reports are available through the VC Functional Safety Manager, and the Z01X fault simulation solution offers a complete fault model set to meet ISO 26262 fault injection testing requirements.
“As security threats for connected vehicles grow, integrating the combination of safety and security features at the SoC level helps minimize the risk of malicious attacks and data breaches in automotive systems,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “Synopsys’ new ARC SEM130FS and tRoot HSM for Automotive integrate both specific hardware safety features and security features to enable designers to meet ISO 26262 requirements and protect vehicle sensitive data and communications.”
Synopsys’ broad DesignWare IP portfolio includes logic libraries, embedded memories, IOs, PVT sensors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Extensive investment in IP quality and comprehensive technical support enable designers to reduce integration risk and accelerate time-to-market.