Serial memory controller for data centre computing
The SMC 1000 8x25G allows CPUs and other SoCs to access four times the memory channels of parallel attached DDR4 DRAM in the same footprint. The serial memory controllers feature higher memory bandwidth and media independence with ultra-low latency.
SMC 1000 8x25G interfaces to the CPU through 8-bit Open Memory Interface (OMI)-compliant 25 Gbps lanes and bridges to memory through a 72-bit DDR4 3200 interface. This results in a reduction in the number of host CPU/SoC pins for each DDR4 memory channel. The controller is the first memory infrastructure product from Microchip that uses the media-independent OMI interface.
Microchip’s SMC 1000 8x25G has a low latency design that allows under 4 ns incremental latency to the first DRAM data access and identical subsequent data access performance. This results in OMI-based DDIMM products having virtually identical bandwidth and latency performance to comparable LRDIMM products.
The controller comes with design-in collateral and ChipLink diagnostic tools that provide extensive debug, diagnostics, configuration and analysts tools with an intuitive GUI.