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RISC-V Foundation’s Rick O’Connor interview

Interviews |
By eeNews Europe


“RISC-V (pronounced five) was really the result of a summer academic program to create a processor that could be used to teach processor design in 2010,” O’Connor explained. The obvious choices for teaching had been the x86 and ARM but their instruction sets had become complicated and there were IP and license issues so using them for teaching was not really possible. The the primary motivation was for something simple but that used the best ideas for academia. It took until 2013 to develop and May 2014 was when the specification was first frozen.

But the reason that RISC-V Foundation was formed to look after the ISA specification was because companies liked the open-ness and wanted to make use of the architecture in the commercial environment, O’Connor added. “There are now more than 100 organizations in the RISC-V Foundation. We call it an open instruction set architecture rather than open-source hardware. It’s not the first. SPARC is open and there have been others.”

And that is an important distinction because although ISA is open and use of it is royalty free there is a lot of work to be done creating an implementation of that ISA; in creating a full-blown CPU from an ISA. The companies that do that work – such as SiFive, Cortus, GreenWaves, Microsemi and others – will want paying for it just as you pay a microcontroller vendor whether it is based on ARM or another ISA.

So why would a user go for a RISC-V based chip rather than a more established architecture?

Next: Clean-slate architecture


“Well, it’s a clean-slate ISA that benefits from 30 years or more of research. We’ve kept what’s good and got rid of what was less successful. It’s also very tight, clean, small and modular. That means you can take the things you want and leave out what you don’t need. And because it’s open it is also extensible,” said O’Connor.

There are four simple base instruction sets RV32I, RV32E, RV64I and RV128I along with modular extensions denoted by letters M A F D Q C. More can be found out here Linley Group: RISC-V offers simple, modular ISA. It is worth noting that RISC-V already has an approach for 128bit addressing.

Given that there have been other efforts in open hardware, why now, we asked?

“There’s been a shift in how people architect processors. This is because Moore’s Law is not producing its traditional performance and power benefits. We’ve seen it for a while giving rise to the use of accelerator hardware and multi-node clusters for performance,” O’Connor said. It is also notable that a couple of post-ARM contender architectures – ARC and Tensilica were absorbed into the IP offerings of EDA companies Synopsys and Cadence, respectively, where their configurability has formed the basis of numerous application-specific hardware accelerators.

O’Connor added that RISC-V is modular and includes a generous user-defined developer space. And is a return to RISC principles with simple instructions that execute in a single cycle. The modularity means that many designs, particularly at the low end, can achieve significant die area savings, and likely power savings, compared with processors based on older ISAs.

O’Connor said: ” Really it’s a different model. It’s the modularity and that there are so many more degrees of freedom. You don’t have to carry the whole specification.”

Next: Two examples


O’Connor gave two examples of RISC-V in use. One was Nvidia which decided in 2015/2016 to replace the proprietary 32bit Falcon microcontroller inside its GPUs with a 64-bit RISC-V-based reinterpretation. Falcon stands for Fast Logic Controller. “Clearly Nvidia is engineering savvy and they will ship millions of these chips,” said O’Connor.

The second user is the mass storage company Western Digital that, through a history of acquisitions had ended up with a broad range of storage media, capacities and applications and used a dozen different ISAs. From a memory controller in a USB stick up to RAID server. Martin Fink, CTO at Western Digital is a visionary who is interested in memory-oriented development and wanted to use RISC-V to engage in some one-stop shopping.

But again Western Digital is an engineering-rich company that could license in architectures to design with, develop its own, or use RISC-V. For both companies using RISC-V was clearly the lowest-cost option.

But that doesn’t make it an easy choice for those building systems around processor chips. ARM, MIPS and x86 all have a well-established ecosystems. “Well, the RISC-V ecosystem is young but it is growing. We have doubled the number of member companies from a year ago,” said O’Connor pointing to the number of companies on the RISC-V Foundation booth

We asked O’Connor whether RISC-V architecture need to be extended to cope with the interest in machine learning and neural networks.

O’Connor argued that the extensibility of the RISC-V architecture means it is already good for machine learning. “We’re not missing out on ML or AI; we’re enabling it,” he said.

This again provides a nice sandbox for hardware and software engineers to play in which may be good for some commercial companies but others will want a proven route, short time to market and the assurance that their chosen RISC-V approach will be maintained and supported.

Next: Task groups


“We are an open foundation with working groups and standardization committees that can focus on a particular approach if the members want. We have groups working on vector extensions and DSPs, which are the building blocks of machine learning. There is also a very active security task group working on things like encryption and trusted root of computation.” O’Connor admitted that RISC-V Foundation right now is somewhat better at opening task groups than it is at closing them out.

“RISC-V doesn’t have a silver bullet but we discuss these things openly and rigorously. And when it comes to security users of RISC-V can be confident there are no hidden instructions that they don’t know about but that somebody else might be able to exploit. There are plenty of hidden instructions in x86, fewer in ARM,” said O’Connor.

In short, RISC-V has made a promising start and there are incentives for numerous companies from semiconductor components through to development support to get involved as they can reduce their cost by not paying a royalty on the developer of the ISA.

And RISC-V can provide leaner and potentially lower power solutions at the low-end. This is advantage that diminishes as performance goes higher and cache memories start to dominate die area. And there is still plenty of ground to be covered in areas such as security and alternative computing support.

Related links and articles:

www.riscv.org

Linley Group: RISC-V offers simple, modular ISA

News articles:

ARM’s John Ronco on IP for embedded

Startup plans 4k RISC-V cores on 7nm chip

SiFive launches Linux-ready RISC-V quad-core processor


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