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Renesas chooses Andes RISC-V 32-Bit CPU cores for ASSPs

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By Ally Winning

The two companies have formed a technology IP cooperation. Andes Technology supplies both RISC-V based embedded CPU cores and the associated SoC development environment.

“Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA) for system-on-chips (SoC),” said Frankwell Lin, President of Andes Technology Corp. “This marks the arrival of the open-source RISC-V ISA as a mainstream computing engine. Renesas customers will benefit from a modern ISA constructed for the needs of 21st century computing.”

“The scalable range of performance, selectable safety features, and customization options provided by the Andes RISC-V core IP enables Renesas to provide innovative solutions for future application-specific standard products,” said Sailesh Chittipeddi, Executive Vice President, General Manager of Renesas’ IoT and Infrastructure Business Unit. “Customers looking for cost-effective alternative paths for existing or emerging applications will benefit from the reduced time to market and lower development costs.”

The combination of Renesas’ pre-programmed ASSP devices which will be based on Andes RISC-V core architecture and the specialized user interface tools that are used to set the application programmable parameters, will offer developers full and optimized solutions. The capability will get rid of the initial RISC-V development and software investment barrier for customers. Renesas will look to build a wide network of regional partners that have the specialized expertise to provide cutting edge and focused customer support.

More information

https://www.andestech.com

https://www.renesas.com/eu/en/

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