Renesas bets on SG-MONOS for MCUs with over 100MB of embedded flash

Renesas bets on SG-MONOS for MCUs with over 100MB of embedded flash

Technology News |
A year after it had announced the functional operation of its split-gate metal-oxide nitride oxide silicon (SG-MONOS) 3D flash memory at IEDM 2016, Renesas implemented it as an embedded flash memory array and confirmed the device's operation at a large-scale.
By eeNews Europe

Share:

The company is adamant is has achieved significant progress towards the realization of large-capacity flash memories (100MB or more) to be embedded directly into next-generation MCUs fabricated at the 16 and 14nm nodes.

Cross sectional TEM image of a FinFET SG-MONOS.
Schematic structure of Renesas’ FinFET SG-MONOS.

In the MONOS structure, each memory cell consists of three layers—oxide, nitride, and oxide—on a silicon base, with a metal control gate at the top. The Split-Gate MONOS memory performs its data storage in a thin charge trap film formed on the surface of the silicon substrate, which makes it comparatively easier to deploy it in a fin structure with a three-dimensional structure.

It is highly compatible with 16/14nm logic processes that have the same fin structure. The SG-MONOS flash is said to exhibit excellent charge retention characteristics, not degraded even when the fin structure is introduced.

The challenge when incorporating this fin structure SG-MONOS flash memory cell in a 16/14nm generation MCU is the increase in sample-to-sample variations associated with increasing the memory capacity, notes Renesas who says that for the manufacture of its working prototype, it was able to optimize the process conditions, including the deposition, etching, and ion implantation conditions, for the fin structure, reducing sample-to-sample variations.


Built-in Flash memory array.

Using an optimized step pulse write method (ISSP: incremental step pulse programming) in which the write voltage is increased in steps starting at a low voltage, Renesas claims it was able to obtain faster write and erase operations than with earlier planar structures, with almost no influence on write/erase speed even after 250,000 rewrite cycles. The prototype was also tested to maintain a guaranteed storage time of at least ten years at 160°C after programming.

The company is now working on combining high-performance/low-power state-of-the-art logic with large-capacity/high-performance non-volatile memory implemented with finer feature sizes.

Currently, Renesas mass produces MCUs fabricated in a 40nm generation process using SG-MONOS structure flash memory, it is also developing 28nm generation MCUs. The company plans to develop 16/14nm generation MCUs which may become commercially available around 2023 for practical applications.

Renesas Electronics Corporation – www.renesas.com

 

Related articles:

SGVC 3D NAND architecture could easily reach 6Gb/mm2 says Macronix

IMEC reports nanowire FET in ‘vertical’ SRAM

Intel outlines 3D NAND transition

Leti’s 5nm node to stack Si nanowires

Linked Articles
eeNews Embedded
10s