Reference and simulator models for RISC-V

Reference and simulator models for RISC-V
Technology News |
Latest additions further extend the range of RISC-V projects based on the open standard RISC-V ISA for applications from MCUs to AI and HPC.
By Jean-Pierre Joosting

Share:

Offered as freely available, open-source reference models for the RISC-V community and as commercial products, they now support the latest ratified extensions: Bit Manipulation, Cryptographic (scalar), and Vector, plus the Privilege Specification enhancements. These latest additions further extend the range of RISC V projects based on the open standard RISC V ISA (Instruction Set Architecture) targeted at optimized solutions in applications that range from microcontrollers and application processors, through to multicore arrays for AI (Artificial Intelligence), Machine Learning, and HPC (High Performance Computing).

Specifically, the simulator and reference models support the latest RISC-V Extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0 plus Privilege Specification 1.12 as RISC-V Board formal approval is completed.

Imperas simulation products and tools are supported with open-source processor and platform models licensed under Apache 2.0 via the Open Virtual Platforms initiative and available at OVPworld.org. To assist the rapid development of a virtual platform/prototype, these models and platforms can be modified and further extended as required. The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP application programming interfaces (APIs). The full range of 300+ processor models is based on over 12 ISAs to support heterogeneous designs or for projects migrating other architectures to RISC V.

The Imperas RISC-V reference models are used for design verification (DV) of RISC-V processors and for virtual platforms/prototypes to support software development and test throughout the design cycle. The RISC-V community is supported with multiple free-to-use options, including riscvOVPsim, riscvOVPsimPlus, and riscvOVPsimCOREV. Additionally, the Imperas commercial products are available with professional support plus extra features for more complex designs. They can also integrate within other standard EDA environments, such as SystemC, SystemVerilog, and well-known simulation and emulation tools from Cadence, Siemens EDA, and Synopsys, plus the cloud-based simulation offering from Metrics Technologies.


“An ISA specification is probably the most important interface in computer science; it defines the boundary between the software program and the underlying hardware,” said Simon Davidmann, CEO, Imperas Software Ltd. “RISC-V is the first broadly adopted open standard ISA with many independent implementations. Unlike the single-source developments of the past, RISC-V is community-based with both open-source and proprietary commercial supporters.”

riscvOVPsim is the entry-level free RISC-V model available on GitHub at: github.com/riscv-ovpsim.

riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator), an envelope reference model that can be configured to cover all of the newly ratified RISC-V specifications and standard extensions. Also included are several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open-source and released under the flexible Apache 2.0 open-source license. All models, virtual platforms and example models are available to the RISC-V community via the Open Virtual Platforms website at: www.ovpworld.org/riscvOVPsimPlus.

riscvOVPsimCOREV is a free RISC-V reference model and simulator (ISS) targeted at software developers for the OpenHW CORE-V family of processors. With a proprietary freeware license from Imperas, which covers free commercial and academic use, the simulator package includes a complete open-source model licensed under Apache 2.0. It is available on GitHub for download at: github.com/openhwgroup/riscv-ovpsim-corev.

www.imperas.com

Linked Articles
eeNews Embedded
10s